中国电机工程学报
 
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Proceeding of the CSEE  2020, Vol. 40 Issue (14): 4559-4568    DOI: 10.13334/j.0258-8013.pcsee.191385
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Synchronous Reference Frame Design and Small-signal Model of Frequency-locked Loop
QUAN Xiangjun1, HUANG Renzhi1, WU Zaijun1, TANG Chenghong2, DOU Xiaobo1, HU Qinran1
1. School of Electrical Engineering, Southeast University, Nanjing 210096, Jiangsu Province, China;
2. NARI Research Institute, NARI Technology Co., Ltd., Nanjing 210003, Jiangsu Province, China
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